In the current sub-20 nm technology, 3D multi-gate devices (FinFETs or Tri-gate devices) are mainstream structures, which improve gate control capability and suppress current leakage and Short Channel Effects (SCEs).
Compared with, for example, conventional single-gate bulk Si or SOI MOSFETs, dual-gate SOI based MOSFETs can suppress the SCEs and the Drain Induced Barrier Lowering (DIBL) effect, have a lower junction capacitance, achieve a lightly-doped channel, adjust a threshold voltage by setting a work function of a metal gate, increase a driving current by a factor of about 2, and reduce the requirement on Equivalent Oxide Thickness (EOT). Compared with the dual-gate devices, the tri-gate devices have a gate surrounding the top surface and both side surfaces of the channel, thereby achieving more powerful gate control capability. Further, all-around nanowire multi-gate devices are more advantageous.
The existing method for manufacturing a FinFET structure comprises: etching a bulk Si or SOI substrate to form a plurality of fins and trenches extending in parallel along a first direction; filling the trenches with an insulating material to form Shallow Trench Isolation (STI); depositing a thin (only 1-5 nm, for example) dummy gate insulating layer (generally, silicon oxide) on top and sidewalls of the fins, and depositing a dummy gate layer (generally, polysilicon or amorphous silicon) on the dummy gate insulating layer; etching the dummy gate layer and the dummy gate insulating layer to form a dummy gate stack extending along a second direction which is preferably perpendicular to the first direction; forming a gate spacer at opposite sides of the dummy gate stack in the first direction by deposition and etching; etching portions of the fins at opposite sides of the gate spacer in the first direction to form source/drain trenches, and epitaxially growing source/drain regions in the source/drain trenches; depositing an Inter-Layer Dielectric (ILD) layer on the wafer; removing the dummy gate stack by etching and leaving a gate trench in the ILD layer; and depositing, in the gate trench, a gate insulating layer of a High-k (HK) material and a gate conductive layer of metal/metal alloy/metal nitride.
On the other hand, with scaling down of the devices, the driving capacity is greatly limited. A feasible solution is to use a material other than Si, for example, Ge, GaAs, InP, GaSb, InAs, InSb or the like. In these materials, carriers such as electrons or holes have mobility significantly greater than that in the Si material, so that the device driving capability increases significantly, which can effectively improve the device performances.
The films of a high mobility material as described above are generally thick bulk layers epitaxially formed on a Si substrate, or thick films which are selectively epitaxially formed on an Si substrate with an isolation structure such as STI or the like. The process of forming these layers of a high mobility material is difficult to be compatible with common CMOS standard processes, and has poor compatibility with the gate-last process of HK gate dielectric/Metal Gate (MG) which is currently the mainstream of the CMOS processes. In addition, the thick film layer with high mobility has problems such as too many defects, unstable performances, poor reliability and the like.